【摘要】 提出了一种准循环低密度校验码的部分并行译码结构,按照该结构设计的译码器可兼容多种码率的准循环低密度校验码,同时适用于规则码和非规则码,因此只需设计1个译码器就可完成不同码率的准循环低密度校验码的译码。在Altera公司的StratixⅡ-EP2S90器件上实现了DTMB标准中3种准循环低密度校验码的译码器。FPGA实现结果表明,与传统的译码方案相比,该译码方案可节省大约45%的逻辑单元。更多还原

【Abstract】 A partially-parallel decoder architecture is proposed,which is not only suitable for different code-rates but also can be used for both regular and irregular quasi-cyclic low-density parity-check(QC-LDPC) codes. Only one decoder is needed for QC-LDPC codes with different code-rates. With the proposed architecture,a decoder for three kinds of QC-LDPC codes in DTMB standard is implemented in FPGA device-Altera StratixⅡ-EP2S90. FPGA implementation results show that about 45% of router requirements can be saved compared to previous architecture.更多还原