【摘要】 通过采用合并字节的预整序单元、全并行的基4运算单元、首级存储单元外置的移位延时整序结构和逐级 扩充字长的定点算法,用FPGA实现了一个超高速的基4全并行流水线FFT处理器;在66MHz时钟频率下,处理速度可 达到256K点／ms。更多还原

【Abstract】 The FPGA implementation of a ultra high speed pipelined FFT processor is presented in this paper. A modified input buffering technique, the parallel radix 4 computation unit, the shift delay commutator with the first stage outside FPGA, and the fixed point arithmetic with word length increasing for every stage are designed for the processor. By use of 66Mhz clock,the processor can perform 256K point FFT in 1 ms.更多还原