【摘要】 详细分析了TAGTREE编码规则及其在JPEG2000中的应用,采用固定存储器地址映射关系实现子父节点对应关系的方法简化了地址发生逻辑,提出一种用于JPEG2000打包的TAGTREE编码VLSI体系结构.在Altera公司Stratix系列芯片EP1S25B672C7搭建的FPGA平台上,能够以100MHz时钟频率进行实时打包处理,全部设计只需要消耗628个逻辑单元和128字节的片内存储器.更多还原

【Abstract】 Basic regulations of TAGTREE encoder were investigated and the application of TAGTREE in JPEG2000 was analyzed in detail. A high-performance TAGTREE encoding VLSI architecture in JPEG2000 tier2 encoder was presented. The address generator was simplified by using the method that the address mapping of memory was used to specify the relation between son nodes and father nodes. By using Altera’s stratix EP1S25B672C7 in FPGA platform, this design architecture could work in real time, at the clock frequency of 100MHz,with only 628 logic cells and 128 bytes memory consumed.更多还原