【摘要】 传统数字频率计由于在高频段受基准时钟频率的限制,其测频精度受到很大的限制.本文应用EDA技术,很好的解决了这一问题.文中论述了数字频率计的设计原理、开发环境、设计步骤、设计框架,以及应用VHDL语言对系统的实现方法,说明了各模块和系统输入输出信号的功用.应用MAX+PLU SⅡ对系统进行仿真验证,结果表明所设计的数字频率计不但测频精度达到较高的水平,而且能够实现连续不间断测频.更多还原

【Abstract】 The precision of traditional digital cymometer is prodigious limited by the norm clock frequency,especially in the high frequency band,but this problem is good resolved in here from using the EDA technology.In this paper,the digital cymometer’s design principle and process,exploit environment,frame work and realization method by VHDL are discussed in detail,and the modules and input/output signals’ function are explained particularly.By emulational validate in MAX+PLUSⅡ,we can see that the digital cymometer’s precision has reached to a higher level,and it can realize uninterrupted frequency count.更多还原