【摘要】 文章系统地研究了符号定点高速乘法器的实现算法和结构,采用了修正布斯算法,华莱士压缩树,4:2压缩器,伪4:2压缩器以及平方根求和结构。采用VerilogHDL实现了整个乘法器,在单个时钟周期完成一次16位的符号数乘法。为了验证该乘法器的性能,在VertexII-xc2v1000实现了该乘法器,频率可达62.27MHz。每秒钟可完成6227万次16位的符号乘法。更多还原

【Abstract】 This paper provides the design method of a high speed fixed point multiplier. It employs Modified Booth Arithmetic(MBA), Wallace-Tree, 4:2 Compressor, pseudo 4:2 compressor and the Suqare Root Carry-Select Adder. The multiplier has been realization using VerilogHDL, one 16bits multiplication can be performed in a clock. For verifying the performance of the multiplier, the multiplier has beed download into the VertexII-xc2v1000256-4, the frequency can reach 62.27MHz. 62.27 million times multiplication can be accomplished per second.更多还原