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一种并行的有限域乘法器结构

A Parallel Architecture for Computing Multiplication in GF (2~m)

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【作者】 袁丹寿戎蒙恬陈波

【Author】 YUAN Dan-shou,RONG Meng-tian,CHEN Bo (Detp. of Electronic Eng., Shanghai Jiaotong Univ., Shanghai 200030, China)

【机构】 上海交通大学电子工程系上海交通大学电子工程系 上海200030上海200030上海200030

【摘要】 提出了一种并行的有限域GF(2m)乘法器结构.有限域乘法由多项式乘法和模不可约多项式f(x)两步实现.把多项式被乘数和乘数各自平分成3个子多项式,多项式乘法由子多项式的乘法和加法实现.当多项式的度m=500时,与传统的Mastrivito多项式乘法相比,所提出的多项式乘法结构可以减少33.1%的异或门,减少33.3%的与门.为了简化,采用特殊不可约多项式来产生有限域.此有限域乘法器结构适合高安全度的椭圆曲线密码算法的VLSI设计.

【Abstract】 The parallel multiplier architecture over Galois field GF(2~m) was proposed. The finite field multiplication requires two steps: polynomial multiplication and reduction modulo the irreducible f(x). The polynomial multiplicand and multiplicator are equally split into three sub-polynomials, respectively. The polynomial multiplication is performed by sub-polynomial multiplications and additions. When the degree m of the finite field is 500, compared to the traditional Mastrivito polynomial multiplication, it can reduce the number of the XOR gates by 33.1%, and that of the AND gates by 33.3%. To simplify reduction modulo, the special polynomials are used to generate finite field. The proposed multiplier architecture suits elliptic curve cryptosystems with large finite field.

【基金】 国家高技术发展计划(863)资助项目(2003AA141040)
  • 【文献出处】 上海交通大学学报 ,Journal of Shanghai Jiaotong University , 编辑部邮箱 ,2005年04期
  • 【分类号】TN918.3
  • 【被引频次】13
  • 【下载频次】272
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