【摘要】 在分析边界扫描测试技术的工作机制对测试主控系统的功能需求基础上,提出了一种基于PCI总线采用FPGA实现的低成本边界扫描测试主控器的硬件设计方案.该系统以PC机为平台,利用FPGA器件设计实现JTAG主控芯核,并在主控器芯核内加入FIFO,提高了PCI总线的传送速率,使用户能够利用计算机方便的组成一个边界扫描测试系统.经仿真和测试实践表明,该系统产生的测试信号完全满足IEEE1149.1协议的时序要求,对支持IEEE1149.1协议的芯片进行功能测试和PCB板的互连测试及电路故障诊断.该系统结构简单,使用方便,工作可靠.更多还原

【Abstract】 Reviewing the test mechanism of boundary-scan and the functional requirement of boundary-scan tester, this paper presents a hard-ware design project based on PCI-bus boundary-scan master controller by using FPGA. In the system, PC works as a platform, the design adopts FPGA for JTAG IP core and adds FIFO for accelerating the rate in transmission data, so the system is characterized by the whole function, and has a low price. Simulation and practical test results show that the system is feasible, the performance of the test system meets the requirements of IEEE 1149.1. It can be used in the boundary-scan test of IC and PCB, as well as in the chip level integrated circuit of function test and fault modeling. The system has a simple structure, and it is convenient and reliable in use.更多还原