【摘要】 安全散列算法是数字签名等密码学应用中重要的工具。目前最常用的安全散列算法是SHA-1算法,它被广泛地应用于电子商务等信息安全领域。为了满足应用对安全散列算法计算速度的需要,该文提出了一种快速计算SHA-1算法的硬件结构。该方法通过改变硬件结构、引入中间变量,达到缩短关键路径的目的,进而提高计算速度。这种硬件结构在0.18μm工艺下的ASIC实现可以达到3.9Gb/s的数据吞吐量,是改进前的两倍以上;它在FPGA上实现的性能也接近目前SHA-1算法商用IP核的两倍。更多还原

【Abstract】 Secure hash algorithms are important tools for cryptographic applications such as digital signatures. An efficient hardware architecture was developed to speed up the widely used secure hash algorithm SHA-1. The design shortens the critical path by adjusting the iterative method. The optimized ASIC implementation delivers 3.9 Gb/s of processing throughput using 0.18 μm CMOS technology, more than twice the speed of a straightforward implementation. The performance on FPGA is nearly twice as fast as most commercial IP cores for SHA-1.更多还原