【摘要】 文章介绍了流水线电压型结构A/D转换器的一种改进设计。该6位A/D转换器采用6个相同的处理单元级联,每个处理单元(内部倍乘作差单元统一设计)对所输入的模拟信号进行量化,输出一位数字信号,并把经该级处理后剩下的量化噪声信号传入下一处理单元,如此下去,直至最后一个处理单元。电路采用0.6μm双阱、双多晶硅、双金属线的标准CMOS工艺实现,芯片面积为2.05 mm×1.95 mm=3.9975 mm2,共有28个I/O管脚。更多还原

【Abstract】 A voltage scaling A/D converter with improved pipeline architecture is presented in the paper.The 6-bit A/D converter is structured by cascading 6 identical stages,each of which quantizes sampled analog signals from the previous stage and outputs one bit of the digital code as well as the residue signal to the next stage until(the last one The chip is fabricated in 0.6 μm standard CMOS process(twin well,double poly and double metal).)The die area is 3.9975 mm~2(2.05 mm×1.95 mm),with 28 I/O pads.更多还原