【摘要】 基于控制流图数据流图层次模型,以分支覆盖、位功能覆盖以及语句可观测覆盖为目标,给出一个高层测试用例生成算法,并最终实现一种可行的RTL级测试生成算法.实验结果表明,在较少的测试生成时间下,该法可生成相对短的测试序列,得到与其他方法相当或略差的测试效果.此外,该算法因采用了测试用例技术而具良好的灵活性.更多还原

【Abstract】 As a primary part of design verification and chip testing in the life cycle of Integrated Circuits (ICs), test generation receives increasing attention. By the application of branch coverage, bit-function coverage and statement-observability coverage measures, this paper introduces a high level test case generation method based on Control Flow Graph?Data Flow Graph (CFG?DFG) model, and then puts forward a feasible test generation method at Register Transfer Level (RTL). Experimental results demonstrate that the method can produce shorter test sequence in less time, and obtains an equal or a little less stuck-at fault coverage at gate-level. Furthermore, the method provides sufficient flexibility due to the adoption of test case technique.更多还原