【摘要】 通过分析嵌入式Cache存储器中使用的双端口字定向静态存储器 (SRAM )和内容可寻址存储器 (CAM )的功能故障模型 ,提出了有效地针对嵌入式应用的DS MarchCE和DC MarchCE测试算法 ,解决了以往算法用于嵌入式系统时故障覆盖率低或测试时间长导致测试效率低的问题 利用MarchCE算法并结合Cache系统的电路结构特点 ,设计并实现了一套集中管理的内建自测试测试方案 此方案可以并行测试Cache系统中不同容量、不同端口类型的存储器 ,并且能够测试地址变换表 (TLB)的特殊结构 ,测试部分面积不到整个Cache系统的 2 %更多还原

【Abstract】 Based on the analysis of functional fault models of dual-port word-oriented SRAM and CAM used in embedded caches, efficient DS-March CE test algorithm and DC-March CE test algorithm aiming at embedded applications have been presented. These new algorithms are a good tradeoff between fault coverage rates and test periods in solving the problems of inefficient tests that happen in testing embedded caches when the previous algorithms were directly applied. Using March CE algorithms and taking the characters of cache circuit into account, a centralized BIST test scheme is designed and implemented. With overhead area less than 2%, this scheme is able to simultaneously detect the faults of the memories with various capacities and port categories, as well as the special structure of TLB.更多还原