【摘要】 随着数字信号处理器主频的不断提高,其中的运算单元已由单层流水线结构向多层流水线结构变迁。但随之带来了访问内存时出现等待周期的问题。文章提出了读写分层及硬件写回缓冲的设计,消除了访存单元等待周期,使访存单元获得100%的工作效率。更多还原

【Abstract】 During the increment of the main frequency of digital signal processor, the arithmetic module is divided into multi-level. But it causes the problem of memory access wait cycle. The paper proposes a design which arranges reading andwriting access in different pipeline level and introduces a write-back buffer to eliminate the memory access wait cycle, andthen the memory access unit can achieve100% workefficiency.更多还原