【摘要】 文中针对Montgomery模乘算法进行了分析和改进,采用了一种理想的适合于硬件实现的Montgomery算法。根据此算法提出了一种新的脉动阵列结构,有效降低了芯片的面积,提高了模乘的运算速度。基于CMOS的0.6um工艺下,模乘器VLSI实现共用9k个等效门,最高工作时钟频率可达100MHz,完成1024位Montgomery模乘约需4295个时钟周期。更多还原

【Abstract】 This paper analyzes and improves the algorithm of Montgomery.A novel systolic array modular multiplier is presented based on the modified Montgomery algorithm which is ideally suitable for hardware-inplementation.The modular multiplier effectively reduced its size and greatly increased its speed.Operating at maximum clock frequency up to 100MHz,it takes about 4295 clock cycles to accomplish a 1024-bit Montgomery modular multiplication.Using 0.6um CMOS technology,it holds about 9k gate counts.更多还原