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块浮点算法在数字脉冲压缩中的应用
Implementation of Digital Pulse Compression Using Block-floating-point Arithmetic
【摘要】 应用块浮点算法设计并实现了某雷达接收机数字脉冲压缩系统,着重阐述了块浮点部件的设计原理与实现,并对块浮点、定点算法中截断误差对数字脉冲压缩的影响进行了计算机仿真分析.脉压系统使用FPGA实现,可完成1024点和256点脉压处理,最快时间分别为57.70s和12.65s.
【Abstract】 Presents a Digital Pulse Compression (DPC) system which has beenused in some Radar receiver. The design and implementation of Block-floating-point components are especially illustrated in detail. Error analysis was given by computer simulation. The compression process can be achieved in 57.70 s for 1 024-point DPC or in 12.65 s for 256- point DPC.
【关键词】 数字脉冲压缩;
块浮点;
信噪比;
截断误差;
FPGA;
【Key words】 Digital Pulse Compression (DPC); Block-floating-point; SNR; truncation error; FPGA;
【Key words】 Digital Pulse Compression (DPC); Block-floating-point; SNR; truncation error; FPGA;
- 【文献出处】 河北工业大学学报 ,Journal of Hebei University of Technology , 编辑部邮箱 ,2005年04期
- 【分类号】TN78
- 【被引频次】12
- 【下载频次】209