【摘要】 提出了基于CPLD(复杂可编程逻辑器件 )实现傅立叶变换点数可灵活扩展的高速FFT处理器的结构设计以及各功能模块的算法实现,包括高组合数FFT算法的流水线实现结构、读 /写RAM地址规律、补码实现短点数FFT阵列处理结构以及补码实现CORDIC(坐标旋转数字计算机 )算法的流水线结构等,输入数据速率为 20MHz时, 1024点FFT运算时间约为 50us。更多还原

【Abstract】 The architecture of scalable length and high speed FFT processor based on CPLD(Complex Programmable Logic Device) is proposed, including the pipeline architecture of the radix mixed FFT algorithm, the address regularity of the read-then-write RAM, the array architecture of short-length FFT and the pipeline complement architecture of CORDIC(Coordinate Rotation Digital Computer) algorithm. If the input-data velocity is 20 MHz,the time expended on 1024-point FFT is 50 us.更多还原