【摘要】 介绍了一种单片集成的3.125 Gb/s接收器的设计,它适用于IEEE 802.3ae四通道10 Gb/s以太网接口.电路采用了多相时钟结构和并行采样技术以降低电路速度要求.电荷泵采用了常跨导偏置技术以降低环路对工艺、电源电压和温度变化的敏感度.时钟数据恢复电路采用1/5速率时钟降低振荡器的设计难度,时钟恢复的同时完成1:5解串功能,降低了电路功耗.电路采用0.18μm CMOS工艺设计和仿真,总体功耗为95 mW,625 MHz恢复时钟的输出抖动小于75 ps,电路在3.125 Gb/s的数据率和各种工艺角下工作正确.更多还原

【Abstract】 The design of a monolithicintegrated 3.125 Gb/s receiver for IEEE802.3ae quad channel 10 Gbit Ethernetinterfaceis described.The multiphase clockgenerator and parallel sampling phase detector are usedtoreducethespeedre-quirement.Self-biased constant-gmbiasing technique is used for charge-pump phase-locked loop(PLL) to achieve lowsensitivity tothe variationof environments.The clockand datarecovery(CDR) circuit exploits 1/5-rate clocktechniquetofacilitate the design of the ring oscillator and eli minate the need of 1∶5 demultiplxer,thereby achievinglowpower con-sumption.The circuit has been designed and si mulated in 0.18μm CMOS process.The power dissipationis 95 mW,while thetotal jitter of recoveredclockat 625 MHzislessthan75 ps.The circuit works well at 3.125 Gb/s datarate andall process corners.更多还原