【摘要】 在Booth算法的基础上,提出了一个适用于多媒体加速单元(Multimedia Accelerator) 的乘法器IP核设计。通过增加一位符号位,本设计支持32×32无符号和有符号乘法。通过一个32×9结合2 bit Booth算法阵列乘法器循环四次加法,完成32bit乘法。前四个时钟周期,每次处理一个9bit乘法,后两个周期分别处理低32 bit和高32 bit加法。我们采用2.5 V, 0.25μm SMIC CMOS工艺,实现乘法器的设计,其中部分积求和部分和ALU单元,Hspice仿真的最大延迟分别为0.64 ns,1.51 ns。更多还原

【Abstract】 This paper describes a 32×32 Multiplier IP which is used for Multimedia Accelerator. The multiplier supports both signed and unsigned integer multiplication by a additional sign bit.The 32×9 partial product terms are summed up in parallel at the first 4 cycles .The low 32-b result and the high 32-b result are formed by a carry-select adder at the last 2 cycles. We implement the proposed multiplier with 0.25 μm SMIC CMOS technology, at a supply voltage of 2.5 V. The latency of the Partial-product adder and the ALU unit are 0.64 ns,1.51 ns respectively.更多还原