【摘要】 在2位超前进位加法器的基础上,引入了流水线结构,设计了一种8位流水线加法器,极大地提高了加法器的运算速度,减少了加法指令的CPU占用时间,并对加法器的关键结构锁存器设计从逻辑功能和电路结构上进行了详细讨论,证明本设计的可行性。更多还原

【Abstract】 In this paper, a pipelined structure is introduced based on 2-bit carry look-ahead adder. The type of 8-bit pipelined carry look-ahead adder can improve the add operation speed to a large extent and can reduce the CPU’s occupation of the add instruction as well. As for the adder’s key structure, the latch, the logical function and circuit structure of it is discussed in detail, which proves the practicability of the very design demonstrated in the paper.更多还原