【摘要】 在集成电路设计中,功能验证是主要的瓶颈之一。据估计,验证工作占设计工作开销的 60%以上。Synopsys公司VMT(Vera验证模型技术)工具可减小验证的工作量、节约时间。文中描述了使用VMT对USBD(通用串行总线器件)模块的验证,验证了USBD部件符合协议规范、完成系统定义的要求,并对不同的数据传输方式进行比较。本设计已通过MPW(multi projectwafer)流片生产出实际芯片,其效果在实际的芯片上得到了验证,达到了设计的效果。更多还原

【Abstract】 Functional verification is one of the narrowest bottlenecks in fast design of integrated circuits. It is estimated that verification in its entirety consumes up to 60% of design resources. Synopsys supplied VMT(Vera model technology) can reduce the work amount of verification .In this paper, we illustrate the use of VMT for USBD(USB device) and verify that the USBD module complies with universal serial bus specification and runs in accordance with the system specification. The design method resulted in the production of real chip through MPW (multi-project wafer). Moreover, the result achieved the expected target demostated by the verification of actual chip prototype.更多还原