【摘要】 结合用于CMOS图像传感器中的低噪声DPGA的性能特点,提出了一种优化电容阵列拓扑结构的方法,讨论了此种结构下由寄生电容引入的时钟馈通和电荷分配效应,并给出了仿真结果和按照0.35μmCMOS工艺进行流片的版图。测试结果表明,采用改进的电容阵列结构能把采样电容引入的噪声斜率从原来的0.15降低到0.01。更多还原

【Abstract】 This paper is based on the high performance characteristic of the low noise digital programmable gain amplifier(DPGA) usually used in the CMOS image sensor . The proposed method to optimize the capacitor segment and reduce the noise induced by the parasitic capacitor has been discussed. We also presented the simulation result and the layout designed using 0.35 μm CMOS technology. The simulation result indicated that the noise slope reduced from 0.15 to 0.01.更多还原