【摘要】 提出了DVB通用解扰算法高性能IP核设计、验证和测试的方法,着重描述了IP核的可重用设计,使本IP核与多种总线能互连。整个设计采用VHDL语言设计,在Altera的FPGA和富士通CE66库上进行了综合和验证。最终在富士通CE66库上实现的IP核最高时钟频率为212.8MHz,数据率可以达到1.7024Gbps。更多还原

【Abstract】 An efficient method of the implementation, verification and test about DVB common descrambling algorithm proposed, and especially it focuses on the reuse design of the IP Core. This IP Core can freely interconnect with multifarious bus architectures. The whole design is described with VHDL, synthesized and verified not only on the FPGA of Altera but also on CE66 library of Fujustu. The final core implementation using CE66 library of Fujustu can work at a data rate up to 1. 7024 Gbps (212.8MHz).更多还原