【摘要】 提出了一种基于仿真 (simulation- based)的 32位 RISC微处理器的功能验证方法 .以伪随机生成和针对流水线模型生成激励向量方式相结合为主的验证环境的建立 ,提高了功能验证的自动化程度和效率 ;同时采用代码覆盖率来分析和指出功能验证中的遗漏之处 ,从而提高了整个验证环境的完备性 .另外 ,通过 FPGA硬件验证的结果以及 32位RISC微处理器流片的测试结果 ,可以证明本文所提出的功能验证方法的有效性和完备性更多还原

【Abstract】 This paper presented a simulation based functional verification methodology to validate a 32 bit RISC microprocessor (named as FDU32 below). In the scheme, pseudo random generation and pipeline focus generation are used as the main method to generate testbenches, and based on this the whole verification environment is set up to improve the automation and efficiency of the process. In addition, in order to guarantee the quality of the verification, code coverage analysis is used to evaluate and direct the effort of the verification. By the FPGA verification result and FDU32 chip functional testing result, the validity and the completeness of the functional verification methodology is proven.更多还原