【摘要】 RS编码器IP核设计的难点是提高编码电路的编码运算速度。采用基于多项式乘法理论的GF(2m)上4位快速有限域乘法的方法,提高了编码电路中乘法器模块的运算速度,并对传统的编码电路进行优化,从而解决了运算速度慢的问题。使用VerilogHDL语言和Verilog7.0软件,设计了RS(15,9)编码器,通过仿真及软、硬件验证了设计的正确性。更多还原

【Abstract】 The difficulty of RS encoder IP core design is how to improve operation rate of encoding circuit. This paper introduces four bites rapid multiplication based on the multinomial multiplicative theory of Galois to improve the operation rate of multiplication module whereby the problem of slow operation speed is solved. Verilog HDL and software of Verilog7.0,are used to design RS (15,9) encoder.Finally,the design correctness is tested via the simulation results and software and hardware.更多还原