【摘要】 针对复旦大学自主开发的32位RISCCPU,设计了相应JTAG调试电路(In-CircuitEmulator)。为解决此RISCCPU中5级流水线导致的断点误停的问题,提出了一种新颖的带有分支预测功能的电路结构─“流水线追踪器”。此JTAG调试电路与IEEE1149.1标准兼容,具有设置断点、单步、查看或修改CPU寄存器/内存空间、在线FLASH编程等多种功能。更多还原

【Abstract】 A design of JTAG debugging circuit for the 32-bit RISC CPU is presented and a novel circuit architecture with the ability of branch predicting -"pipeline tracer" is depicted to solve breakpoint halt error by the multi-stage pipeline of the RISC CPU. The debugging circuit is compatible with the IEEE standard 1149.1. Its feature includes: Breakpoint, Single step, View or modify CPU register/memory space, in-circuit FLASH programming.更多还原