【摘要】 采用新型三维云纹干涉系统并结合盲孔释放的方法 ,研究了半导体装配底座内的残余应力 ,这种混合的方法不仅能真实测试试件因应力的释放而产生的三维变形信息 ,而且具有灵敏度高、条纹对比度好等特点。本文中 ,残余应力是通过盲孔释放获得 ,然后使用三维干涉系统来测试试件因残余应力的释放而发生的位移 ;利用有限元模拟的方法 ,精确计算了应力大小和分布情况 ,为实验研究提供了有力的支持和补充。结果表明 ,残余应力在F - 1C半导体内部分布不均匀 ,在两引脚之间的区域 ,应力比邻近区域的应力要大 ,存在一定的应力集中 ,对可伐管产生一定的挤压作用 ,这是造成半导体装配底座失效的一重要原因。更多还原

【Abstract】 A combined method of 3-D Moiré interferomety system and incremental hole drilling to study residual stresses distribution in the semiconductor is presented. The hybrid method can’t only obtain the in-plane and out-of-plane displacement produced by the residual stress relaxation in practice, but also has the advantages: of high sensitivity, spatial resolution and high contrast for the fringe patterns of the displacement fields. In this paper, the residual stress is obtained by incremental hole drilling directly, and then a new 3-D Moiré interferomety system is employed to obtain the in-plane and out-of-plane deformation. The finite element simulation is performed to calculate the values and distribution of stresses and to provide the support and complementarities for experimental measurement. The results indicate that unsymmetrical residual stress distributions exist in the F-1C semiconductor devices. There is a concentration of the residual stress in the area between the two pins, that is the stress values in the area are higher than that in its vicinity. The stress concentration will press the pins and result in the failure of the F-1C semiconductor devices.更多还原