【摘要】 针对基于MIPS核的高清晰度电视(HDTV)的片上系统,设计了一种EC总线控制器。在MIPS核外采用高速缓存来提高总线效率。实现了流水线总线事件,解决了EC总线时钟与外设时钟的转换。通过MIPS总线功能模块(BFM)的时序仿真验证了该控制器的正确性。0.25-μmCMOS工艺综合了EC总线控制器的RTL代码,总线时钟可达到149MHz。最后通过了FPGA验证。更多还原

【Abstract】 An EC bus controller of high definition television (HDTV)based on MIPS IP core is presented.Adopting high-speed buffer out of MIPS core is to enhance the performance of the EC bus.Pipeline bus transaction is realized.The conversion between the EC bus clock and the peripheral clock is implemented.Timing and function simulation are performed by the bus functional module(BFM) provided by MIPS Technologies Inc.The RTL code of the bus controller is synthesized for 0.25-μmCMOS technology.Finally,the design is tested by FPGA.更多还原