【摘要】 文章采用全开关状态的延时单元和双延时路径两种电路技术设计了一种高工作频率、低相位噪声的环形振荡器.环路级数采用偶数级来获得两路相位相差90℃的正交输出时钟.采用TSMC0.18μmCMOS工艺进行流片,电压控制振荡器(VCO)的频率范围为4.9～5.5GHz,模拟的相位噪声为-119.3dBc/Hz@5M,采用1.8V电源电压,核芯电路的功耗为30mW,振荡器核芯面积为60μm×60μm.更多还原

【Abstract】 This paper presents two circuit techniques of full switching delay cells and dual-delay path to design a high operate frequency, low noise ring oscillator. An even-stage ring oscillator is adopted to generated two quadrature output clock of 90 degrees phase differences. The chip is fabricated in 0.18 μm CMOS process, VCO operates at 4.9 GHz to 5.5 GHz, the simulated phase noise is -119.3 dBc/Hz at 5 MHz offset. With the 1.8 V-power supply, the core circuit power is 30 mW, the chip core area is 60 μm×(60 μm.)更多还原