【摘要】 根据单片机一线制扩展的特点,在EDA软件ISE的环境下,利用VHDL语言建立一线制IP核。此设计利用状态机实现,并下载到芯片通过硬件试验验证,可以解决ONE WIRE器件和单片机接口读写时序严格的问题,从而解决了一线制通信器件应用问题.满足不同场合的需求。更多还原

【Abstract】 This paper mainly describes the one wire IP core realization based on CPLD. On the basis of the characteristic of microcomputer extension, on the condition of EDA software ISE, in the VHDL language, complete the one wire IP core. By the state-machine get the aim of the design, furthermore the program has been downloaded into the CPLD and validate the conclusion, and it can be used in different fields through the exploitation of the interface circuit and the program of software.更多还原