【摘要】 在某些特殊应用场合 ,如数据采集 ,现场可编程逻辑器件 ( FPGA)需要借助微处理器来完成与上位机的数据通信 ,设计基于 FPGA实现的通信接口电路 IP核将大大提高 FPGA器件的应用灵活性。本文以 SCI通信接口电路为例详细阐述了接口电路的结构、工作原理 ;提出了基于复杂时序电路状态机嵌套的设计思想。给出了 SCI接口电路的 VerilogHDL语言描述及 Xilinx ISE 6.1 i平台下的仿真结果更多还原

【Abstract】 Under some special circumstances, such as data acquisition, FPGA device needs MCU to implement the data communication with an upper-machine. The design of IP core of communication interface based on FPGA will greatly improve the application flexibility of FPGA. This paper takes the SCI interface as an example and gives the structure and principle of SCI interface. The idea of nesting state-machine based on complex timing circuit is proposed and the hardware description of SCI interface by Verilog HDL is introduced. The simulation waveform under Xilinx ISE 6.1i platform is also proposed in this paper.更多还原