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用CPLD实现的高精度脉冲干扰抑制电路
Design of pulse disturbance restriction circuit with CPLD
【摘要】 提出了一种用CPLD实现的高精度新型脉冲干扰抑制电路。仿真分析和实际应用结果表明,该电路简单可靠,能有效地抑制数字信号中的脉冲干扰,明显提高电路的抗干扰能力,保证数据传输的可靠性,是一种有实用价值和重复利用潜力的电路。
【Abstract】 A new design of circuit with pulse disturbance restriction based on CPLD is presented.The result of simulation analysis and application demonstrates that the disturbance restriction ability of this CPLD circuit is greatly improved,and the data transmission reliability is guaranteed.The circuit has practicality and popularization.
【关键词】 脉冲干扰;
CPLD;
电力线载波通信;
【Key words】 pulse disturbance; Complex Programmable Logic Device; power line carrier communication;
【Key words】 pulse disturbance; Complex Programmable Logic Device; power line carrier communication;
- 【文献出处】 电力系统通信 ,Telecommunications For Electric Power System , 编辑部邮箱 ,2004年06期
- 【分类号】TN792
- 【被引频次】1
- 【下载频次】57