节点文献
80位并行3D-DCT硬件核解决方案
80 Bit-Paralleled Three-Dimensional DCT Core Solution
【摘要】 提出一种使用三维离散余弦变换 ( 3D DCT)对运动图像进行压缩解压的新算法 .在此算法的基础上构造了一个 80位 3D DCT硬件核 ,通过并行连乘连加运算加快计算速度、三维转置存储体消除矩阵转置耗时、中间寄存器消除中间计算结果的存取时间等综合手段 ,达到高速处理目的 .FPGA实现的时序模拟表明 ,采用这种算法可以对现有制式的电视图像进行实时压解处理 .
【Abstract】 This paper proposes a new algorithm on motion pictu re compression and decompression using Three-dimensional Discrete Cosine Transfor m. The algorithm not only emphasizes reducing computation but also helpful with hardware implementation. Based on this approach, an 80 bit-parallelled 3D-DC T hardware is developed, which uses parallel multiplication to accelerate comput ation ,three-dimensinal transposition memory to remove the time consumption of transposition operation and temporary register to reduce the time of accessing i ntermediate values. FPGA simulations show that real time video 3D-DCT compressi on can be completed by using the hardware core.
【Key words】 D-DCT; 80 bit-paralleled multiplication and add core; real time compression and decompression; FPGA;
- 【文献出处】 中国科学技术大学学报 ,Journal of University of Science and Technology of China , 编辑部邮箱 ,2003年01期
- 【分类号】TN919.81
- 【下载频次】39