【摘要】 介绍的 8位可编程外设接口 (PPI)IP的设计 ,就在概要介绍该PPI基本功能的基础上 ,详细描述了该PPI电路的控制通路和数据通路设计 ,电路的功能仿真 ,综合 ,以及验证等过程 .设计的后仿真波形以及FPGA验证结果表明 ,该IP核能满足Intel815 5H和 82 5 5A芯片的功能和时序要求 ,而且可以根据应用需求进行裁剪 ,方便的用于所需的系统设计中 .更多还原

【Abstract】 It is well known that a system can be integrated into a single chip. The problems confronting designers are becoming increasingly complex. The key challenges include the increasing density and complexity in deep sub-micron design, testing and product quality and time-to-market demand and so on. Design reuse becomes the main resolution of system design. It is necessary to develop a reusable IP library .We can explore this method by the IP designing of a 8-bit PPI(Programmable Peripheral Interface). In this paper, we introduce the control path and data path design of the PPI current, functional simulation, synthesis, post-simulation, and. Verification. The post-simulation wave and FPGA verification result show this IP core can meet the functional specification and timing characters of the Intel 8155H and 8255A . The IP core can also be configured to meet the application requirement when integrated into a system on chip.更多还原