【摘要】 设计实现了一种用于多视点三维图像压缩的三维离散余弦变换(3DDCT)。该电路结构需要3N2/2个乘法器和5N2/2+7N/2个加法器来实现N×N×N点DCT运算。为了提高系统处理效率,电路采用了流水线结构,数据吞吐率为N点每周期。整个电路采用模块化的设计方法,并用Verilog硬件描述语言对所设计电路的功能进行了仿真验证。更多还原

【Abstract】 A new 3D DCT architecture for the computation of the three-dimensional discrete cosine transform(3D DCT)for compression of integral3D images is proposed.The architecture uses3N 2 /2multiplier and5N 2 /2+7N/2adder to evaluate N×N×N-point DCT and yields results at a rate of N point per cycle.In order to improve the efficiency of the system,the pipeline structure is used.The design of the3D DCT is modeled in RTL level by verilog HDL and simulated by Cadence verilog_XL.更多还原