【摘要】 本文阐述了一个 1 2 8× 32 bits的三端口寄存器堆的高速低功耗设计 ,说明了分块结构的确定、存储单元的改进以及其他部分电路的设计。在 TSMC0 .2 5 μm CMOS工艺下实现版图的设计 ,并在 2 .5 V工作电压下进行了后仿真。该寄存器堆的工作频率最高可达 5 0 0 MHz,功耗约为 5 5 mw。更多还原

【Abstract】 In this paper, the architecture of divided SRAM array and the modified cell structure are implemented in the three-port register file for high speed and low power.The layout in TSMC 0.25μm CMOS technology has been completed.Simulation results in 2.5v show that it has a top frequency of 500MHz.Power dissipation is about 55mw.更多还原