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一种新颖的集成电路版图验证方法
A New Method for Layout Verification of Integrated Circuits
【摘要】 版图验证是集成电路设计的瓶颈之一。文章全面系统地阐述了超大规模集成电路LVS版图验证的原理、方法和基本的流程,着重介绍了基于Dracula开发的CMOS、Bipolar和ABCD(AdvancedBipolarCMOSDMOS)工艺的LVS命令文件,在解决以上工艺的电路LVS的过程中,取得了令人满意的效果。
【Abstract】 Methods for layout verification of LVS of VLSI’s are described in detail Its principle and basic flow are presented A set of LVS rule files for CMOS, Bipolar and advanced bipolar CMOS DMOS (ABCD) has been developed in Dracula language These files have been used in layout verifications of LVS based on CMOS, Bipolar and ABCD processes, and satisfactory results have been achieved
【关键词】 VLSI;
LVS;
版图验证;
Dracula语言;
LDMOS;
【Key words】 VLSI; Layout versus schematic (LVS); Layout verification; Dracula language; LDMOS;
【Key words】 VLSI; Layout versus schematic (LVS); Layout verification; Dracula language; LDMOS;
- 【文献出处】 微电子学 ,Microelectronics , 编辑部邮箱 ,2003年02期
- 【分类号】TN402
- 【被引频次】12
- 【下载频次】303