【摘要】 随着VLSI设计的发展 ,设计师时常需要面临不同时钟域之间信号传输和异步复位 /置位等情况 ,在这类情况下 ,电路就有可能出现亚稳态。为此首先介绍了亚稳态的特性 ,以及处理亚稳态的一种解决方案 ,D触发器在亚稳态下的特性。提出了一种减少亚稳态出现可能性的D触发器单元的设计方案 ,并使用H SPICE进行了仿真更多还原

【Abstract】 As the developing of VLSI design, the engineers must be confronted with the situation of signal transfer between different clock domain and asynchronous set/reset occasionally. In this situations, metastability may occur. In this paper, there is a introduction of metastability behavior, then providing a method for dealing with it, and a introduction of D type flip flop design for reducing the disaster which metastability bring forth.更多还原