【摘要】 根据监视跟踪定时器的工作原理,介绍了一种实用看门狗电路的VerilogHDL设计及CPLD实现方法,结构简单、功能完善,可与任何综合库、工艺库以及FPGA/CPLD芯片结合开发出用户需要的门级网表和芯片版图,易于移植。文中还介绍了针对复杂数字系统的FPGA/CPLD开发设计的流程。更多还原

【Abstract】 The principle of supervising and monitoring operation of computer controlling system is discussed in detail in this paper. A practical Watch-Dog Timer circuit is designed in VerilogHDL, which is implemented in FPGA/CPLD. A procedure for FPGA/CPLD design is also introduced which is useful for large-scale digital system especially.更多还原