【摘要】 采用现场可编程门阵列 (FPGA) ,设计了一种用于SDH传输系统中数据通信通道 (DCC)数据帧汇聚与速率适配的电路 .可以将具有不同时钟的 1 2个独立DCC通道中的HDLC数据帧进行提取、缓存并复接成一个时分复用的高速数据链路 ,交给MotorolaMPC860中的多通道通信控制器进行处理 .整个设计采用一片XILINX的xc2s2 0 0pq2 0 8完成 ,使用约 1 7万等效门 ,在HDLC最大帧长为 1kB的情况下 ,允许的多通道通信控制器与DCC通道时钟之间的时钟偏差大于 1 4%,并给出了测试波形更多还原

【Abstract】 This paper presents a new method used in SDH transmission systems to converge the HDLC data frames from 12 independent data communication channels (DCC) into one time division multiplexing data link. HDLC packets from DCC channels with different clocks can be abstracted, buffered, and inserted into different timeslots of a high speed data link and sent to the multi channel HDLC controller embedded in the Motorola MPC860 processor. The design is implemented with an XILINX xc2s200pq208 and approximately 170?000 equivalent gates are possessed. With HDLC packet length less than 1 kbytes, the tolerance of clock difference between the multi channel HDLC controller and DCC channels can exceed 1 4%. The tested waveform is presented.更多还原