【摘要】 本文重点研究通用视频处理器(VSP)中运动估计协处理器的设计。该设计提出了一种将常用的并行SIMD结构与流水线MISD结构相结合的新颖并行视频处理体系结构形式。协处理器中各个模块单独设计,经由指令调用来实现不同的算法。兼顾到不同格式视频序列的通用性以及灵活性等要求,协处理器可以同时激活最多8个同类模块并行协同工作以实现对不同格式图像块的处理。该设计结构非常简单,易于实现。目前,已经通过VSP芯片整体的指令级与功能级仿真与验证。结果表明,当系统时钟为80MHz时,运动估计协处理器与VSP的其它功能部件及指令部件可以有机协调地工作。更多还原

【Abstract】 Design process of video motion estimation coprocessor for VSP is discussed. In this process, a unique parallel video processing architecture combined with SIMD and pipeline MISD is proposed. Modules within the coprocessor are designed individually. Different algorithms can be realized by different combination of instructions. Video sequences with different size and format can be processed by several (up to 8) activated identical modules cooperating in parallel. The designed architecture can be easily implemented. Both instructional and functional simulation for the whole VSP show that this motion estimation coprocessor works correctly with other functional components of VSP under the system clock rate up to 80 MHz.更多还原