【摘要】 研究了Pb₃O₄对（Co,Nb）掺杂SnO₂压敏材料电学性质的影响,当Pb₃O₄的含量从0.00增加到0.75％（摩尔分数,下同）时,（Co,Nb）掺杂SnO₂压敏电阻的击穿电压从426 V/mm迅速减小到160V/mm,40 Hz时的相对介电常数从1240迅速增加到2760.这说明Pb₃O₄是调控SnO₂压敏材料击穿电压和介电常数的敏感添加剂,晶界势垒高度测量表明,在实验范围内Pb的含量对势垒高度的影响很小,随着Pb含量的增加,SnO₂的晶粒尺寸的迅速长大是击穿电压迅速减小和介电常数迅速增大的主要原因,对样品的复阻抗进行了测量,发现未掺杂Pb的样品具有最低的晶界电阻,而掺杂0.50％Pb₃O₄的样品具有最高的晶界电阻.提出了一个修正的缺陷势垒模型,指出了替代Sn的受主不应当处于晶界上,而应处于耗尽层的Sn的晶格位置.更多还原

【Abstract】 The effect of Pb3O4 on the varistor and dielectric properties of the Sn02 ceramics was investigated. It was found that the breakdown voltage of Sn02-based varistors decreased from 426 V/mm to 160 V/mm, and the relative dielectric constant at 40 Hz of the SnO2-based varistors increased from 1240 to 2760 with increasing Pb3O4 concentration from 0 to 0.75%, which shows that Pb3O4 is a sensitive dopant to regulate the breakdown voltage and the dielectric constant of the Sn02-based varistors. Measurement of the barrier heights at grain boundaries showed that the Pb3O4 concentration in this experimental range had a less influence on the barrier heights. The increase of the Sn02 grain size with increasing Pb3O4 concentration from 0 to 0.75 mol% is the reason for lowering the breakdown voltage and raising the dielectric constant. The impedance measurement of SnO2-based varistors shows that the varistor without doping Pb has the lowest grain-boundary resistance and the varistor doped with 0.50% Pb3O4 presents the highest grain-boundary resistance. A modified defect barrier model was introduced, in which the electronegative acceptors substituting for Sn ions should not be located at the grain interfaces but at SnO2 lattice sites of depletion layers instead.更多还原