节点文献
JPEG2000 EBCOT编码器的VLSI结构设计
VLSI Architecture of EBCOT Encoder for JPEG2000
【摘要】 采用并行运算和动态内存控制DMC(dynamicmemorycontrol)的结构完成了EBCOT(em-beddedblockcodingwithoptimizedtruncation)编码器的VLSI设计.在保证编码速度的前提下,最大限度降低了片内存储器的访问频率,同时将片内小波系数缓存量减少了60%以上.在200MHz的工作主频下,每秒可以完成20帧分辨率为1024×1024×24比特图像的JPEG2000编码.该E-BCOT编码器已经作为单独的IP核应用于目前正在开发的JPEG2000图像编解码芯片中.
【Abstract】 Proposes a VLSI architecture of EBCOT, in which a Dynamic Memory Control (DMC) is adopted to reduce 60% scale of the on-chip wavelet coefficients storage. A parallel architecture is proposed to speed-up the coding process. This architecture can be used as a compact and efficient IP core for JPEG2000 VLSI implementation and various real-time image/video applications.
- 【文献出处】 北京邮电大学学报 ,Journal of Beijing University of Posts and Telecommunications , 编辑部邮箱 ,2003年04期
- 【分类号】TN76
- 【被引频次】18
- 【下载频次】217