【摘要】 提出了一个新的用于 10 / 10 0 Base- T以太网中面积和功耗优化的时钟恢复电路 .它采用双环路的结构 ,加快了锁相环路的捕获和跟踪速度 ;采用复用的方式 ,通过选择信号控制电路可分别在 10 Mbps或 10 0 Mbps模式下独立工作且能方便地实现模式间的互换 ,与采用两个独立的 CDR电路相比节省了一半的面积 ;同时 ,电路中采用一般的延迟单元来取代 DL L,并能保证环路性能不随工艺温度等条件引起的延迟单元、延迟时间的变化而变化 ,从而节省了功耗 .Hspice模拟结果显示 ,在 Vdd=2 .5 V时 ,10 0 Mbps模式下电路的功耗约为 75 m W,稳态相差为 0 .3 ns;10 Mbps模式时电路功耗为 5 8m W,稳态相差为 0 .9ns更多还原

【Abstract】 A power and area efficient CMOS clock recovery circuit designed for the 10/100 base-T ethernet is described.The dual-loop structure is adopted to expedite the capture and track progress;With a control signal,the CRC circuit can work in 10Mbps or 100Mbps mode and easy to change from one state to another so that save the chip area compared to using two circuits working in single mode separately.The traditional DLL circuit is substituted by normal delay-cell,and the whole circuit performance will not be degraded by the variation of delay time arising from different technique and temperature condition and then the power dissipation will be saved.The simulation by Hspice shows that the IC consumes 75mW in 100Mbps mode with a jitter less than 0.3ns and 58mW in 10Mbps mode with a jitter less than 0.9ns from a 2.5V supply.更多还原