节点文献
适于SoC的统一设计语言SystemVerilog
SystemVerilog—a unified design language for system-on-chip
【摘要】 顺应SoC的发展趋势,Accellera标准组织提议了一个统一设计语言SystemVerilog。本文主要讨论了SystemVerilog的特点、设计优势、现状和未来趋势等,并给出了一些实例。SystemVerilog是C、C++、Superlog和Verilog的混合,它极大地扩展了抽象结构层次的设计建模和验证的能力,是SoC设计的最佳统一语言。
【Abstract】 With the trend of SoC design, a unified design language,SystemVerilog, isbeing proposed by Accellera. An overview of SystemVerilog is provided, including features,advantages, current status and future plan. Some examples are presented. SystemVerilog is a blendof C, C++, SUPERLOG and Verilog, which greatly extends the ability to model and verify designs atan abstract architectural level. It is a best unified design language for SoC.
- 【文献出处】 半导体技术 ,Semiconductor Technology , 编辑部邮箱 ,2003年12期
- 【分类号】TN402
- 【被引频次】13
- 【下载频次】268