节点文献
MPEG2视频解码器VLSI结构研究
A Study on the VLSI Structure of the Video Decoder for MPEG2
【摘要】 介绍了MPEG2视频解码器的VLSI实现方法,采用ASIC结构实现MPEG2标准的视频解码,用流水线哈佛结构RISC型微控制器对视频数据流、变字长解码以及电路时序进行控制,提高了电路速度,减小了芯片面积。
【Abstract】 The VLSI implementation of an MPEG2 video decoder is proposed, in which ASIC structure is used to realize video decoding in MPEG2 standard. Video bitstream, VLD and circuit sequence for the decoder are controlled by an RSIC microcontroller with pipelined Harvard structure. By using the proposed technique, processing speed of the circuit is improved and chip area is reduced.
- 【文献出处】 微电子学 ,MICROELECTRONICS , 编辑部邮箱 ,1998年03期
- 【分类号】TN47
- 【下载频次】64