【摘要】 开关级快速时域模拟器ＦＴＳＩＭ（ＦａｓｔＴｉｍｉｎｇＳＩＭｕｌａｔｏｒ），可对ＭＯＳＬＳＩ／ＶＬＳＩ数字电路进行逻辑功能和时间特性的模拟与验证；基于波形松弛算法，ＦＴＳＩＭ首先将电路分解成直流连通单元（ＤＣＣ），然后利用晶体管非线性模型按一定次序计算每个ＤＣＣ的输出波形。在求解该模型特征方程的过程中，采用了电压步进方法，同时提出了处理ＤＣＣ之间反馈问题的事件驱动自适应窗口算法。ＦＴＳＩＭ可以充分利用电路的多速率特性和各类休眠特性来提高分析速度，测试结果表明，对于中规模的ＭＯＳ数字电路，速度比ＳＰＩＣＥ提高２～３个数量级，而波形偏差约５％；并且速度提高随着被分析电路规模的增大而近似线性增加。由于被分析电路采用晶体管级描述，ＦＴＳＩＭ可以用于分析门级和开关级逻辑，ＤＯＭＩＮＯ结构等ＭＯＳ电路，也可直接用于验证从集成电路版图中提取的ＭＯＳ数字电路。更多还原

【Abstract】 This paper presents a switch level fast timing simulator FTSIM to verify the logical behaviour and timing performance for MOS digital circuits of both prelayout and post-layout.Circuits are first partitioned into DCCs(DC-Connected Component),then the charging and discharging of each output node of a DCC is modeled by a macromodel retaining the nonlinearity of transistors and its characteristic equation is computed by a voltage incremental technique.Besides,a heuristic eventdriven self-adaptive window algorithm is proposed to speed up waveform convergence when feedbacks present at DCC level.Testing results with benchmark circuits from industry show a speedup of 2 to 3 orders of magnitude over SPICE for medium scale circuits with typical 5% timing accuracy loss,and the speedup is nearly linear up with the circuit size.更多还原