【摘要】 本文提出了把任意。维嵌套循环算法映射和划分到２维固定大小的Ｓｙｓｔｏｌｉｃ阵列的一种自动设计方法．由于考虑了数据相关性，运用该方法产生的ＶＬＳＩ算法的执行时间少，而且不会引起时空冲突．因为平面ＶＬＳＩ阵列容易构造，所以该方法有良好的可行性和实用性．更多还原

【Abstract】 In this paper, an automatic designing method is suggested for mapping and partitioning arbitrary η-dimensional nested loop algorithms onto 2-dimensional fixed-size Systolic array. Since data dependencies are already taken into consideration, any VLSI algorithm generated by this approach 11as less execution time and remains space-time conflict free. Planar VLSI arrays are easy to construct, so the method has good feasibility and applicability.更多还原