【摘要】 本文对多值时序逻辑电路提出了一种新的设计思想:以连续逻辑中不同的逻辑电平来表示时序机状态集中的不同状态及其他参数集中的不同元素;以电容及其旁路MOS管代替触发器实现信号的暂存和抹除.由于取消了传统的以一个二进制码代表一种状态的方法,使设计过程大大简化,可以使用多值时序电路的通用模块.实现不同的时序函数只需改变模块中某几个接点,所以设计、制造和使用都很方便.更多还原

【Abstract】 A new idea of logic design for the multiple-valued synchronous sequential machine is presented. Each state in the state set of the sequential machine or each element in the parameter set is represented by a certain logic value, instead of a binary code, as in the classical design. Capacitors and their bypass MOS transistors are used for the storage and erasure of signals, instead of using flip-flops. Thus, the design of synchronous sequential machine appears extremely simple. One can use the universal modular block to realize the multiple-valued sequential machine. For different sequential functions, the circuit construction is identical, only some connecting points need to be changed, so it is convenient for design, production and application.更多还原