【摘要】 VHDL硬件描述语言及其设计环境是一个形式化、层次化和规范化的计算机硬件描述与设计语言系统,它的出现为实现计算机设计领域的科学化迈出了重要的一步。本文较详细地介绍了VHDL的起因、历史和现状,概要地论述了VHDL语言及其语言特征,并讨论了VHDL的设计环境,最后提出了实现该系统的基本途径。更多还原

【Abstract】 VHDL hardware description language along with its design environment is a language system with formal, hierarchical and canonical features for computer hardware description, documentation and design. The emerging of the VHDL language has made an important step towards the systematization of computer design. This paper describes in detail the origin, development and current status of VHDL, summarizes the VHDL language and its various language features, and discusses the design environment of VHDL. Basic approaches to implementing a minimum system in the VHDL design environment are also presented.更多还原