【摘要】 本文提出了一种新型开关电容模拟迟返线的设计。这一新的设计充分有效地利用了时钟脉冲,达到了可能的最大工作速率。更多还原

【Abstract】 Analogue delay line is necessary and required in signal proces-sing such as in transversal filters,lattice filters,programmable filters,ad-aptive filters,ect,and it is conventionally realized with CCD-technology;but the emergence of switched capaeitor technology has provided an alternat-ive,i.e.,SCADL (Switched Capacitor Analogue Delay Line).Presentedin this paper is a new design of SCADL,each stage of which has unit delayand needs only one op-amp.In this design,the full potential of clock rate isdug out and the highest operation speed is gained for the given componentsor integration process.The experimental results show that this SCADL demo-ates excellent characteristics such as large signal handling capability and lowdistortion.更多还原