【摘要】 <正> 一、引言 时延模型是逻辑模拟、开关级模拟、定时模拟以及定时分析与验证中的基本问题。目前时延模型大多为经验式的。其分析结果与实际电路时延相差很大。实际电路时延特性的复杂性是造成这种情况的主要原因,晶体管尺寸、阈值电压、基元互联、负载电容、输入波形,以及晶体管在电路中的使用方式等因素都将影响电路的时延。 本文在作者近来工作的基础上,提出了基于时延势概念的一种理论上自洽的时延建模方法,所得模型简单,精度较以往时延模型提高,从而为节点时延势方程理论的实用化奠定了基础。更多还原

【Abstract】 Based upon a newly defined signal delay time and a signal dalay potential concept, a novel technique named piecewise modeling(PWM) of MOS VLSI digital circuits is presented in this paper. In this approach, a further consideration in terms of physics can be given on how input waveform slope, threshold voltage, output capacitor load, and etc. affect the delay of MOS digital circuits. Also, When PWM is used in the analysis of practical MOS digital circuits, more precise solutions caa be easily obtained, and the relative error is controlled under 5% compared with the SPICE results.更多还原